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| w wm8198 (8 + 8) bit output 16-bit cis/ccd afe/digitiser wolfson microelectronics plc w :: www.wolfsonmicro.com production data, june 2004, rev 4.0 copyright ? 2002 wolfson microelectronics plc description the wm8198 is a 16-bit analogue front end/digitiser ic which processes and digitises the analogue output signals from ccd sensors or contact image sensors (cis) at pixel sample rates of up to 6msps. the device includes three analogue signal processing channels each of which contains reset level clamping, correlated double sampling and programmable gain and offset adjust functions. three multiplexers allow single channel processing. the output from each of these channels is time multiplexed into a single high-speed 16-bit analogue to digital converter. the digital output data is available in 8 or 4-bit wide multiplexed format. an internal 4-bit dac is supplied for internal reference level generation. this may be used during cds to reference cis signals or during reset level clamping to clamp ccd signals. an external reference level may also be supplied. adc references are generated internally, ensuring optimum performance from the device. using an analogue supply voltage of 5v and a digital interface supply of either 5v or 3.3v, the wm8198 typically only consumes 195mw when operating from a single 5v supply. features ? 16-bit adc ? 6msps conversion rate ? low power ? 212mw typical ? 5v single supply or 5v/3.3v dual supply operation ? single or 3 channel operation ? correlated double sampling ? dual range programmable gain amplifier (9-bit resolution) ? programmable offset adjust (8-bit resolution) ? programmable clamp voltage ? 8 or 4-bit wide multiplexed data output formats ? internally generated voltage references ? 28-pin ssop package ? serial control interface applications ? flatbed and sheetfeed scanners ? usb compatible scanners ? multi-function peripherals ? high-performance ccd sensor interface block diagram rinp data i/o port sen vsmp mclk vrlc/vbias sdi sck dvdd2 timing control cl rlc/acyc rlc v s r s binp ginp vrx vrt oeb m u x vrb rlc rlc cds cds cds 4 configurable serial control interface adc agnd1 dgnd avdd dvdd1 op[0] op[1] op[2] op[3] op[4] op[5] op[6] op[7]/sdo agnd2 m u x vref/bias m u x r g b m u x r g b + pga i/p signal polarity adjust 9 8 pga 9 8 pga 9 8 + + + + + i/p signal polarity adjust i/p signal polarity adjust offset dac offset dac offset dac rlc dac w wm8198
wm8198 production data w pd rev 4.0 june 2004 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 absolute maximum ratings.........................................................................5 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 input video sampling ............................................................................................. 9 output data timing ................................................................................................ 9 serial interface ................................................................................................... 10 device description .......................................................................................12 introduction.......................................................................................................... 12 input sampling ....................................................................................................... 12 reset level clamping (rlc) ............................................................................... 12 cds/non-cds processing ................................................................................... 13 offset adjust and programmable gain....................................................... 14 adc input black level adjust .......................................................................... 14 overall signal flow summary ........................................................................ 15 calculating output for any given input .................................................... 15 output formats .................................................................................................... 16 control interface .............................................................................................. 17 timing requirements ........................................................................................... 18 programmable vsmp detect circuit ............................................................. 18 references............................................................................................................. 19 power supply ........................................................................................................ 19 power management ............................................................................................. 19 line-by-line operation ........................................................................................ 20 operating modes .................................................................................................. 21 operating mode timing diagrams ................................................................... 22 device configuration .................................................................................25 register map .......................................................................................................... 25 register map description ................................................................................. 26 applications information .........................................................................29 recommended external components........................................................... 29 package dimensions ....................................................................................30 address:................................................................................................................... 31 wm8198 production data w pd rev 4.0 june 2004 3 pin configuration sen op[1] op[0] sck sdi dvdd2 op[7]/sdo op[2] op[3] op[4] op[5] op[6] ginp agnd1 vrb vrt vrx vrlc/vbias binp avdd dgnd agnd2 dvdd1 oeb vsmp rlc/acyc mclk rinp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8198cds 0 to 70 o c 28-pin ssop msl1 260 o c wm8198cds/r 0 to 70 o c 28-pin ssop (tape and reel) msl1 260 o c wm8198scds 0 to 70 o c 28-pin ssop (lead free) msl1 260 o c wm8198scds/r 0 to 70 o c 28-pin ssop (lead free, tape and reel) msl1 260 o c note: reel quantity = 2,000 wm8198 production data w pd rev 4.0 june 2004 4 pin description pin name type description 1 rinp analogue input red channel input video. 2 agnd2 supply analogue ground (0v). 3 dvdd1 supply digital supply (5v) for logic and clock generator. this must be operated at the same potential as avdd. 4 oeb digital input output hi-z control, all digital outputs disabled when oeb = 1. 5 vsmp digital input video sample synchronisation pulse. 6 rlc/acyc digital input rlc (active high) selects reset level clamp on a pixel-by-pixel basis ? tie high if used on every pixel. acyc autocycles between r, g, b inputs. 7 mclk digital input master clock. this clock is applied at n times the input pixel rate (n = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). 8 dgnd supply digital ground (0v). 9 sen digital input enables the serial interface when high. 10 dvdd2 supply digital supply (5v/3.3v), all digital i/o pins. 11 sdi digital input serial data input. 12 sck digital input serial clock. digital multiplexed output data bus. adc output data (d15:d0) is available in two multiplexed formats as shown, under the control of register muxop [1:0] see ?output formats? description in device description section for further details. 8+8-bit 4+4+4+4-bit a b a b c d 13 op[0] digital output d8 d0 14 op[1] digital output d9 d1 15 op[2] digital output d10 d2 16 op[3] digital output d11 d3 17 op[4] digital output d12 d4 d12 d8 d4 d0 18 op[5] digital output d13 d5 d13 d9 d5 d1 19 op[6] digital output d14 d6 d14 d10 d6 d2 20 op[7] digital output d15 d7 d15 d11 d7 d3 alternatively, pin op[7]/sdo may be used to output register read-back data when oeb = 0 and sen has been pulsed high. see serial interface description in device description section for further details. 21 avdd supply analogue supply (5v). this must be operated at the same potential as dvdd1. 22 agnd1 supply analogue ground (0v). 23 vrb analogue output lower reference voltage. this pin must be connected to agnd via a decoupling capacitor. 24 vrt analogue output upper reference voltage. this pin must be connected to agnd via a decoupling capacitor. 25 vrx analogue output input return bias voltage. this pin must be connected to agnd via a decoupling capacitor. 26 vrlc/vbias analogue i/o selectable analogue output voltage for rlc or single-ended bias reference. this pin would typically be connected to agnd via a decoupling capacitor. vrlc can be externally driven if programmed hi-z. 27 binp analogue input blue channel input video. 28 ginp analogue input green channel input video. wm8198 production data w pd rev 4.0 june 2004 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max analogue supply voltage: avdd gnd - 0.3v gnd + 7v digital supply voltages: dvdd1 ? 2 gnd - 0.3v gnd + 7v digital ground: dgnd gnd - 0.3v gnd + 0.3v analogue grounds: agnd1 ? 2 gnd - 0.3v gnd + 0.3v digital inputs, digital outputs and digital i/o pins gnd - 0.3v dvdd2 + 0.3v analogue inputs (rinp, ginp, binp) gnd - 0.3v avdd + 0.3v other pins gnd - 0.3v avdd + 0.3v operating temperature range: t a 0 c +70 c storage prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c package body temperature (soldering, 10 seconds) +260 c package body temperature (soldering, 2 minutes) +183 c notes: 1. gnd denotes the voltage of any ground pin. 2. agnd1, agnd2 and dgnd pins are intended to be operated at the same potential. differential voltages between these pins will degrade performance. recommended operating conditions condition symbol min typ max units operating temperature range t a 0 70 c analogue supply voltage avdd 4.75 5.0 5.25 v digital core supply voltage dvdd1 4.75 5.0 5.25 v 5v i/o dvdd2 4.75 5.0 5.25 v digital i/o supply voltage 3.3v i/o dvdd2 2.97 3.3 3.63 v wm8198 production data w pd rev 4.0 june 2004 6 electrical characteristics test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c, mclk = 12mhz unless otherwise stated. parameter symbol test conditions min typ max unit overall system specification (including 16-bit adc, pga, offset and cds functions) conversion rate highspeed = 0, highspeed = 1, mclk = 24mhz 6 12 msps msps full-scale input voltage range, pgamode=0. (see note 1) max gain min gain 0.4 4.08 vp-p vp-p full-scale input voltage range, pgamode=1. (see note 1) max gain min gain 0.6 3 vp-p vp-p input signal limits (see note 2) v in 0 avdd v full-scale transition error gain = 0db; pga[8:0] = 96(hex) 20 mv zero-scale transition error gain = 0db; pga[8:0] = 96(hex) 20 mv differential non-linearity dnl 1.25 lsb integral non-linearity inl 20 lsb total output noise min gain max gain 3.9 11 lsb rms lsb rms channel to channel gain matching 1 % references upper reference voltage vrt 2.85 v lower reference voltage vrb 1.35 v input return bias voltage vrx 1.65 v diff. reference voltage (vrt-vrb) v rtb 1.4 1.5 1.6 v output resistance vrt, vrb, vrx 1 ? vrlc/reset-level clamp (rlc) rlc switching impedance 50 ? vrlc short-circuit current 2 ma vrlc output resistance 2 ? vrlc hi-z leakage current vrlc = 0 to avdd 1 a rlcdac resolution 4 bits rlcdac step size, rlcdac = 0 v rlcstep avdd = 5.0v 0.25 v/step rlcdac step size, rlcdac = 1 v rlcstep 0.17 v/step rlcdac output voltage at code 0(hex), rlcdacrng = 0 v rlcbot avdd = 5.0v 0.39 v rlcdac output voltage at code 0(hex), rlcdacrng = 1 v rlcbot 0.26 v rlcdac output voltage at code f(hex) rlcdacrng, = 0 v rlctop avdd = 5.0v 4.14 v rlcdac output voltage at code f(hex), rlcdacrng = 1 v rlctop 2.81 v vrlc deviation 25 mv offset dac, monotonicity guaranteed resolution 8 bits differential non-linearity dnl 0.1 0.5 lsb integral non-linearity inl 0.25 1 lsb step size 2.04 mv/step output voltage code 00(hex) code ff(hex) -260 +260 mv mv notes: 1. full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. 2. input signal limits are the limits within which the full-scale input voltage signal must lie. wm8198 production data w pd rev 4.0 june 2004 7 test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c, mclk = 12mhz unless otherwise stated. parameter symbol test conditions min typ max unit programmable gain amplifier resolution (pgamode=0) 9 bits gain (pgamode=0) 0] : pga[8 5 66 416 ? v/v max gain, each channel (pgamode=0) g max 7.5 v/v min gain, each channel (pgamode=0) g min 0.74 v/v gain error, each channel (pgamode=0) 1 % resolution (pgamode=1) 9 bits gain (pgamode=1) 511 4 0] : pga[8 1 + v/v max gain, each channel (pgamode=1) g max 5 v/v min gain, each channel (pgamode=1) g min 1 v/v gain error, each channel (pgamode=1) 1 % analogue to digital converter resolution 16 bits speed 6 msps full-scale input range (2*(vrt-vrb)) 3 v digital specifications digital inputs high level input voltage v ih 0.8 ? dvdd2 v low level input voltage v il 0.2 ? dvdd2 v high level input current i ih 1 a low level input current i il 1 a input capacitance c i 5 pf digital outputs high level output voltage v oh i oh = 1ma dvdd2 - 0.5 v low level output voltage v ol i ol = 1ma 0.5 v high impedance output current i oz 1 a digital io pins applied high level input voltage v ih 0.8 ? dvdd2 v applied low level input voltage v il 0.2 ? dvdd2 v high level output voltage v oh i oh = 1ma dvdd2 - 0.5 v low level output voltage v ol i ol = 1ma 0.5 v low level input current i il 1 a high level input current i ih 1 a input capacitance c i 5 pf high impedance output current i oz 1 a wm8198 production data w pd rev 4.0 june 2004 8 test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c, mclk = 12mhz unless otherwise stated. parameter symbol test conditions min typ max unit supply currents total supply current ? active (three channel mode) highspeed = 0 highspeed = 1, mclk = 24mhz 46 72 ma ma total supply current ? active (single channel mode) linebyline = 1 mclk = 12mhz 39 ma total analogue supply current ? active (three channel mode) i avdd mclk = 12mhz 42 ma total analogue supply current ? active (one channel mode) i avdd linebyline = 1 mclk = 12mhz 35 ma digital core supply current, dvdd1 ? active (note1) mclk = 12mhz 2 ma digital i/o supply current, dvdd2 ? active (note1) mclk = 12mhz 2 ma supply current ? full power down mode 300 a wm8198 production data w pd rev 4.0 june 2004 9 input video sampling mclk vsmp input video t per t vsmpsu t vsmph t vsu t vh t rsu t rh t mclkl t mclkh figure 1 input video timing note: 1. see page 14 (programmable vsmp detect circuit) for video sampling description. test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c unless otherwise stated. parameter symbol test conditions min typ max units mclk period t per 83.3 ns mclk high period t mclkh 37.5 ns mclk low period t mclkl 37.5 ns vsmp set-up time t vsmpsu 10 ns vsmp hold time t vsmph 5 ns video level set-up time t vsu 15 ns video level hold time t vh 5 ns reset level set-up time t rsu 15 ns reset level hold time t rh 5 ns notes: 1. t vsu and t rsu denote the set-up time required after the input video signal has settled. 2. parameters are measured at 50% of the rising/falling edge. output data timing mclk op[7:0] t pd figure 2 output data timing wm8198 production data w pd rev 4.0 june 2004 10 oeb op[7:0] t pze hi-z t pez hi-z figure 3 output data enable timing test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c unless otherwise stated. parameter symbol test conditions min typ max units output propagation delay t pd i oh = 1ma, i ol = 1ma 30 ns output enable time t pze 50 ns output disable time t pez 25 ns mclk rlc/acyc pga/offset mux output t acycsu t acych t acycsu t acych figure 4 auto cycle timing test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c unless otherwise stated. parameter symbol test conditions min typ max units auto cycle set-up time t acycsu 10 ns auto cycle hold time t acych 5 ns serial interface sck sdi sen sdo t sper t sckl t sckh t ssu t sh t sce t sew t sec t serd t scrd msb lsb t scrdz adc data adc data register data figure 5 serial interface timing wm8198 production data w pd rev 4.0 june 2004 11 test conditions avdd = dvdd1 = 5.0, dvdd2 = 3.3, agnd = dgnd = 0v, t a = 25 c unless otherwise stated. parameter symbol test conditions min typ max units sck period t sper 83.3 ns sck high t sckh 37.5 ns sck low t sckl 37.5 ns sdi set-up time t ssu 10 ns sdi hold time t sh 10 ns sck to sen set-up time t sce 20 ns sen to sck set-up time t sec 20 ns sen pulse width t sew 50 ns sen low to sdo = register data t serd 35 ns sck low to sdo = register data t scrd 35 ns sck low to sdo = adc data t scrdz 25 ns note: 1. parameters are measured at 50% of the rising/falling edge. wm8198 production data w pd rev 4.0 june 2004 12 device description introduction a block diagram of the device showing the signal path is presented on page 1. the wm8198 samples up to three inputs (rinp, ginp and binp) simultaneously. the device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. each processing channel consists of an input sampling block with optional reset level clamping (rlc) and correlated double sampling (cds), an 8-bit programmable offset dac and a 9-bit programmable gain amplifier (pga). the adc then converts each resulting analogue signal to a 16-bit digital word. the digital output from the adc is presented on an 8-bit wide bi-directional bus, with optional 8 or 4-bit multiplexed formats. on-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. these registers are programmable via a serial interface. input sampling the wm8198 can sample and process one to three inputs through one or three processing channels as follows: colour pixel-by-pixel: the three inputs (rinp, ginp and binp) are simultaneously sampled for each pixel and a separate channel processes each input. the signals are then multiplexed into the adc, which converts all three inputs within the pixel period. monochrome: a single chosen input (rinp, ginp, or binp) is sampled, processed by the corresponding channel, and converted by the adc. the choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. colour line-by-line: a single chosen input (rinp, ginp, or binp) is sampled and multiplexed into the red channel for processing before being converted by the adc. the input selected can be switched in turn (rinp ginp binp rinp?) together with the pga and offset dac control registers by pulsing the rlc/acyc pin. this is known as auto-cycling. alternatively, other sampling sequences can be generated via the control registers. this mode causes the blue and green channels to be powered down. refer to the line-by-line operation section for more details. reset level clamping (rlc) to ensure that the signal applied to the wm8198 lies within its input range (0v to avdd) the ccd output signal is usually level shifted by coupling through a capacitor, c in. the rlc circuit clamps the wm8198 side of this capacitor to a suitable voltage during the ccd reset period. a typical input configuration is shown in figure 6. an internal clamp pulse, cl, is generated from mclk and vsmp by the timing control block. when cl is active the voltage on the wm8198 side of c in , at rinp, is forced to the vrlc/vbias voltage (v vrlc ) by closing of switch 1. when the cl pulse turns off switch 1 opens, the voltage at rinp initially remains at v vrlc but any subsequent variation in sensor voltage (from reset to video level) will couple through c in to rinp. rlc is compatible with both cds and non-cds operating modes, as selected by switch 2. refer to the cds/non-cds processing section. wm8198 production data w pd rev 4.0 june 2004 13 timing control s/h 4-bit rlc dac cl + + - to offset dac rlc cds from control interface s/h v s r s from control interface mclk vsmp rlc/acyc input sampling block for red channel cds c in rinp vrlc/ vbias 2 1 external vrlc vrlcext figure 6 reset level clamping and cds circuitry if auto-cycling is not required, rlc can be selected by pin rlc/acyc. figure 7 illustrates control of rlc for a typical ccd waveform, with cl applied during the reset period. the input signal applied to the rlc/acyc pin is sampled on the positive edge of mclk that occurs during each vsmp pulse. the sampled level, high (or low) controls the presence (or absence) of the internal cl pulse on the next reset level. the position of cl can be adjusted by using control bits cdsref[1:0] (). if auto-cycling is required, pin rlc/acyc is no longer available for this function and control bit rlcint determines whether clamping is applied. figure 7 relationship of rlc pin, mclk and vsmp to internal clamp pulse, cl the vrlc/vbias pin can be driven internally by a 4-bit dac (rlcdac) by writing to control bits rlcv[3:0]. the rlcdac range and step size may be increased by writing to control bit rlcdacrng. alternatively, the vrlc/vbias pin can be driven externally by writing to control bit vrlcext to disable the rlcdac and then applying a d.c. voltage to the pin. cds/non-cds processing for ccd type input signals, the signal may be processed using cds, which will remove pixel-by-pixel common mode noise. for cds operation, the video level is processed with respect to the video reset level, regardless of whether rlc has been performed. to sample using cds, control bit cds must be set to 1 (default), this sets switch 2 into the position shown in figure 6 and causes the signal reference to come from the video reset level. the time at which the reset level is sampled, by clock r s /cl, is adjustable by programming control bits cdsref[1:0], as shown in figure 8. mclk vsmp acyc/rlc or rlcint cl (cdsref = 01) input video 1x x 0x x 0 rgb rgb no rlc on this pixel rlc on this pixel programmable delay rgb wm8198 production data w pd rev 4.0 june 2004 14 mclk vsmp vs r s /cl (cdsref = 00) r s /cl (cdsref = 01) r s /cl (cdsref = 10) r s /cl (cdsref = 11) figure 8 reset sample and clamp timing for cis type sensor signals, non-cds processing is used. in this case, the video level is processed with respect to the voltage on pin vrlc/vbias, generated internally or externally as described above. the vrlc/vbias pin is sampled by r s at the same time as v s samples the video level in this mode; non-cds processing is achieved by setting switch 2 in the lower position, cds = 0. offset adjust and programmable gain the output from the cds block is a differential signal, which is added to the output of an 8-bit offset dac to compensate for offsets and then amplified by a programmable gain amplifier. the 9-bit pga can operate in two modes, a wide gain range (linear on a db scale) mode or a high resolution (linear in v/v) mode. the pga mode is selected by setting the register bit pgamode. the default setting is pgamode=0 which selects the wide gain range mode. figure 9 and figure 10 show the transfer functions of the pga in each mode. the gain and offset for each channel are independently programmable by writing to control bits dac[7:0] and pga[8:0]. figure 9 wide range gain mode (pgamode=0) figure 10 high-res gain mode (pgamode=1) in colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (red green blue red?) by pulsing the acyc/rlc pin, or controlled via the fme, acycnrlc and intm[1:0] bits. refer to the line-by-line operation section for more details. adc input black level adjust the output from the pga should be offset to match the full-scale range of the adc (3v). for negative-going input video signals, a black level (zero differential) output from the pga should be offset to the top of the adc range by setting register bits pgafs[1:0]=10. for positive going input signal the black level should be offset to the bottom of the adc range by setting pgafs[1:0]=11. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 128 256 384 512 gain register code (pga[8:0]) pga gain (v/v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 128 256 384 512 gain register code (pga[8:0]) pga gain (v/v) wm8198 production data w pd rev 4.0 june 2004 15 bipolar input video is accommodated by setting pgafs[1:0]=00 or pgafs[1:0]=01 (zero differential input voltage gives mid-range adc output). overall signal flow summary figure 11 represents the processing of the video signal through the wm8198. v reset v vrlc v 3 cds = 1 cds = 0 rlcext=1 260mv*(dac[7:0]-127.5)/127.5 analog - x + + see parametrics for dac voltages. op[7:0] d 1 digital adc block pga block offset dac block input sampling block d 2 cds, rlcext,rlcv[3:0], dac[7:0], pga[8:0], pgafs[1:0] and invop are set by programming internal control registers. cds=1 for cds, 0 for non-cds v in is rinp or ginp or binp v reset is v in sampled during reset clamp vrlc is voltage applied to vrlc pin v in x (65535/v fs ) +0 if pgafs[1:0]=11 +65535 if pgafs[1:0]=10 +32768 if pgafs[1:0]=0x pga gain a = 416/(566-pga[8:0]) or a= 1+pga[8:0]x4/511 output invert block d2 = d1 if invop = 0 d2 = 65535-d1 if invop = 1 offset dac rlc dac + v 2 v 1 rlcext=0 figure 11 overall signal flow the input sampling block produces an effective input voltage v 1 . for cds, this is the difference between the input video level v in and the input reset level v reset . for non-cds this is the difference between the input video level v in and the voltage on the vrlc/vbias pin, v vrlc , optionally set via the rlc dac. the offset dac block then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0v, producing v 2 . the pga block then amplifies the white level of the input signal to maximise the adc range, outputting voltage v 3 . the adc block then converts the analogue signal, v 3 , to a 16-bit unsigned digital output, d 1 . the digital output is then inverted, if required, through the output invert block to produce d 2. calculating output for any given input the following equations describe the processing of the video and reset level signals through the wm8199. the values of v 1 v 2 and v 3 are often calculated in reverse order during device setup. the pga value is written first to set the input voltage range, the offset dac is then adjusted to compensate for any black/reset level offsets and finally the rlc dac value is set to position the reset level correctly during operation. note: refer to wan0123 for detailed information on device calibration procedures. the following equations describe the processing of the video and reset level signals through the wm8198. input sampling block: input sampling and referencing if cds = 1, (i.e. cds operation) the previously sampled reset level, v reset , is subtracted from the input video. v 1 = v in - v reset ................................................................... eqn. 1 if cds = 0, (non-cds operation) the simultaneously sampled voltage on pin vrlc is subtracted instead. v 1 = v in - v vrlc .................................................................... eqn. 2 if rlcext = 1, v vrlc is an externally applied voltage on pin vrlc/vbias. if rlcext = 0, v vrlc is the output from the internal rlc dac. v vrlc = (v rlcstep ? rlcv[3:0]) + v rlcbot ................................. eqn. 3 v rlcstep is the step size of the rlc dac and v rlcbot is the minimum output of the rlc dac. wm8198 production data w pd rev 4.0 june 2004 16 offset dac block: offset (black-level) adjust the resultant signal v 1 is added to the offset dac output. v 2 = v 1 + {260mv ? (dac[7:0]-127.5) } / 127.5 ..................... eqn. 4 pga node: gain adjust the signal is then multiplied by the pga gain. the pga transfer characteristic varies with the value of the pgamode register bit. if pgamode = 0 (wide gain range pga mode - default): v 3 = v 2 ? 416/(566 - pga[8:0]) ???................................... eqn. 5a if pgamode = 1 (high resolution pga mode): v 3 = v 2 ? (1 + pga[8:0]x4/511).............................................. eqn. 5b adc block: analogue-digital conversion the analogue signal is then converted to a 16-bit unsigned number, with input range configured by pgafs[1:0]. d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} + 32767......... pgafs[1:0] = 00 or 01 eqn. 6 d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} ............................... pgafs[1:0] = 11 eqn. 7 d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} + 65535.................. pgafs[1:0] = 10 eqn. 8 where the adc full-scale range, v fs = 3v output invert block: polarity adjust the polarity of the digital output may be inverted by control bit invop. d 2 [15:0] = d 1 [15:0] ..............................................................(invop = 0) eqn. 9 d 2 [15:0] = 65535 ? d 1 [15:0].................................................(invop = 1) eqn. 10 output formats the digital data output from the adc is available to the user in 8 or 4-bit wide multiplexed formats by setting control bit muxop[1:0]. latency of valid output data with respect to vsmp is programmable by writing to control bits del[1:0]. the latency for each mode is shown in the operating mode timing diagrams section. figure 12 shows the output data formats for modes 1 ? 2 and 4 ? 6. figure 13 shows the output data formats for mode 3. table 1 summarises the output data obtained for each format. mclk 4+4+4+4-bit output ab ab cd 8+8-bit output mclk 4+4+4+4-bit output ab 8+8-bit output ab c d ab figure 12 output data formats (modes 1 ? ? ? ? 2, 4 ? ? ? ? 6) figure 13 output data formats (mode 3) wm8198 production data w pd rev 4.0 june 2004 17 output format muxop[1:0] output pins output 8+8-bit multiplexed 00, 01, 10 op[7:0] a = d15, d14, d13, d12, d11, d10, d9, d8 b = d7, d6, d5, d4, d3, d2, d1,d0 4+4+4+4-bit (nibble) 11 op[7:4] a = d15, d14, d13, d12 b = d11, d10, d9, d8 c = d7, d6, d5, d4 d = d3, d2, d1, d0 table 1 details of output data shown in figure 12 and figure 13. control interface the internal control registers are programmable via the serial digital control interface. the register contents can be read back via the serial interface on pin op[7]/sdo. note: it is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. this ensures that all registers are set to their default values (as shown in table 5). serial interface: register write figure 14 shows register writing in serial mode. three pins, sck, sdi and sen are used. a six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through sdi, msb first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also msb first. each bit is latched on the rising edge of sck. when the data has been shifted into the device, a pulse is applied to sen to transfer the data to the appropriate internal register. note all valid registers have address bit a4 equal to 0 in write mode. sck sen sdi a5 0 a3a2a1a0b7b6b5b4b3b2b1b0 address data word figure 14 serial interface register write a software reset is carried out by writing to address ?000100? with any value of data, i.e. data word = xxxxxxxx. serial interface: register read-back figure 15 shows register read-back in serial mode. read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output msb first on pin sdo (on the falling edge of sck). note that pin sdo is shared with an output pin, op[7], therefore oeb should always be held low when register read-back data is expected on this pin. the next word may be read in to sdi while the previous word is still being output on sdo. wm8198 production data w pd rev 4.0 june 2004 18 sck sen sdi a51a3a2a1a0xxxxxxxx address data word d7 d6 d5 d4 d3 d2 d1 d0 output data word sdo/ op[7] oeb figure 15 serial interface register read-back timing requirements to use this device a master clock (mclk) of up to 12mhz and a per-pixel synchronisation clock (vsmp) of up to 6mhz are required. these clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. mclk to vsmp ratios and maximum sample rates for the various modes are shown in table 4. programmable vsmp detect circuit the vsmp input is used to determine the sampling point and frequency of the wm8198. under normal operation a pulse of 1 mclk period should be applied to vsmp at the desired sampling frequency (as shown in the operating mode timing diagrams) and the input sample will be taken on the first rising mclk edge after vsmp has gone low. however, in certain applications such a signal may not be readily available. the programmable vsmp detect circuit in the wm8198 allows the sampling point to be derived from any signal of the correct frequency, such as a ccd shift register clock, when applied to the vsmp pin. when enabled, by setting the vsmpdet control bit, the circuit detects either a rising or falling edge (determined by posnneg control bit) on the vsmp input pin and generates an internal vsmp pulse. this pulse can optionally be delayed by a number of mclk periods, specified by the vdel[2:0] bits. figure 16 shows the internal vsmp pulses that can be generated by this circuit for a typical clock input signal. the internal vsmp pulse is then applied to the timing control block in place of the normal vsmp pulse provided from the input pin. the sampling point then occurs on the first rising mclk edge after this internal vsmp pulse, as shown in the operating mode timing diagrams. wm8198 production data w pd rev 4.0 june 2004 19 mclk vsmp (vdel = 000) intvsmp posnneg = 1 (vdel = 001) intvsmp (vdel = 010) intvsmp (vdel = 011) intvsmp (vdel = 100) intvsmp (vdel = 101) intvsmp (vdel = 110) intvsmp (vdel = 111) intvsmp posnneg = 0 (vdel = 000) intvsmp (vdel = 001) intvsmp (vdel = 010) intvsmp (vdel = 011) intvsmp (vdel = 100) intvsmp (vdel = 101) intvsmp (vdel = 110) intvsmp (vdel = 111) intvsmp input pins v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s figure 16 internal vsmp pulses generated by programmable vsmp detect circuit references the adc reference voltages are derived from an internal bandgap reference, and buffered to pins vrt and vrb, where they must be decoupled to ground. pin vrx is driven by a similar buffer, and also requires decoupling. the output buffer from the rlcdac also requires decoupling at pin vrlc/vbias power supply the wm8198 can run from a 5v single supply or from split 5v (core) and 3.3v (digital interface) supplies. power management power management for the device is performed via the control interface. the device can be powered on or off completely by setting the en bit and selpd bit low. alternatively, when control bit selpd is high, only blocks selected by further control bits (seldis[3:0]) are powered down. this allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. in line-by-line operation, the green and blue channel pgas are automatically powered down. all the internal registers maintain their previously programmed value in power down modes and the control interface inputs remain active. table 2 summarises the power down control bit functions. en seldpd 0 0 device completely powers down. 1 0 device completely powers up. x 1 blocks with respective seldis[3:0] bit high are disabled. table 2 power down control wm8198 production data w pd rev 4.0 june 2004 20 line-by-line operation certain linear sensors (e.g. contact image sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. in order to accommodate this type of signal the wm8198 can be set into monochrome mode, with the input channel switched by writing to control bits chan[1:0] between every line. alternatively, the wm8198 can be placed into colour line-by-line mode by setting the linebyline control bit. when this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in mono mode (because only one colour is sampled at a time) through the red channel. figure 17 shows the signal path when operating in colour line-by-line mode. rinp sen v smp mcl k v rlc/vbias sdi sck rlc/acyc rlc binp ginp input mux offset mux rlc r g b r g b pga i/p signal polarity adjust 9 rlc dac + configurable serial control interface op[7:0] + 16- bit adc data i/o port 8 offset dac pga mux timing control cl v s r s 4 cds rlc w figure 17 signal path when in line-by-line mode in this mode the input multiplexer and (optionally) the pga/offset register multiplexers can be auto- cycled by the application of pulses to the rlc/acyc input pin by setting the acycnrlc register bit. see figure 4 for detailed timing information. the multiplexers change on the first mclk rising edge after rlc/acyc is taken high. a write to the auto-cycle reset register causes these multiplexers to be reset; selecting the rinp pin and the red offset/gain registers. alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits intm[1:0] to select the desired colour. it is also possible for the input multiplexer to be controlled separately from the pga and offset multiplexers. table 3 describes all the multiplexer selection modes that are possible. fme acycnrlc name description 0 0 internal, no force mux input mux, offset and gain registers determined by internal register bits intm1, intm0. 0 1 auto-cycling, no force mux input mux, offset and gain registers auto-cycled, rinp ginp binp rinp? on rlc/acyc pulse. 1 0 internal, force mux input mux selected from internal register bits fm1, fm0; offset and gain registers selected from internal register bits intm1, intm0. 1 1 auto-cycling, force mux input mux selected from internal register bits fm1, fm0; offset and gain registers auto-cycled, red green blue red? on rlc/acyc pulse. table 3 colour selection description in line-by-line mode wm8198 production data w pd rev 4.0 june 2004 21 operating modes table 4 summarises the most commonly used modes, the clock waveforms required and the register contents required for cds and non-cds operation. mode description cds available max sample rate sensor interface description timing require- ments register contents with cds register contents without cds 1 colour pixel-by-pixel yes 2msps the 3 input channels are sampled in parallel. the signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the adc, giving an output data rate of 6msps max. mclk max = 12mhz mclk: vsmp ratio is 6:1 setreg1: 03(hex) setreg1: 01(hex) 2 monochrome/ colour line-by-line yes 2msps as mode 1 except: only one input channel at a time is continuously sampled. mclk max = 12mhz mclk: vsmp ratio is 6:1 setreg1: 07(hex) setreg1: 05(hex) 3 fast monochrome/ colour line-by-line yes 4msps identical to mode 2 mclk max = 12mhz mclk: vsmp ratio is 3:1 identical to mode 2 plus setreg3: bits 5:4 must be set to 0(hex) identical to mode 2 4 maximum speed monochrome/ colour line-by-line no 6msps identical to mode 2 mclk max = 12mhz mclk: vsmp ratio is 2:1 cds not possible setreg1: 45(hex) 5 slow colour pixel-by-pixel yes 1.5msps identical to mode 1 mclk max = 12mhz mclk: vsmp ratio is 2n:1, n 4 identical to mode 1 identical to mode 1 6 slow monochrome/ colour line-by-line yes 1.5msps identical to mode 2 mclk max = 12mhz mclk: vsmp ratio is 2n:1, n 4 identical to mode 2 identical to mode 2 table 4 wm8198 operating modes notes: 1. in monochrome mode, setreg3 bits 7:6 determine which input is to be sampled. 2. for colour line-by-line, set control bit linebyline. for input selection, refer to table 4, colour selection description in line-by-line mode. wm8198 production data w pd rev 4.0 june 2004 22 operating mode timing diagrams the following diagrams show 8-bit multiplexed output data and mclk, vsmp and input video requirements for operation of the most commonly used modes as shown in table 4. the diagrams are identical for both cds and non-cds operation. outputs from rinp, ginp and binp are shown as r, g and b respectively. x denotes invalid data. mclk vsmp input video op[7:0] (del = 00) 16.5 mclk periods r a r b g a g b b a b b r a r b g a g b b a b b r a r b g a g b b a b b r a r b r a r b g a g b b a b b op[7:0] (del = 01) b a b b r a r b g a g b b a b b r a r b g a g b b a b b r a r b g a g b b a b b b a b b r a r b g a g b op[7:0] (del = 10) g a g b b a b b r a r b g a g b b a b b r a r b g a g b b a b b r a r b g a g b g a g b b a b b r a r b op[7:0] (del = 11) r a r b g a g b b a b b r a r b g a g b b a b b r a r b g b g a b a b b r a r b r a r b g a g b b a b b b a b b g a g b b a b b r a r b r a r b g a g b g a g b b a b b figure 18 mode 1 operation figure 19 mode 2 operation wm8198 production data w pd rev 4.0 june 2004 23 figure 20 mode 3 operation figure 21 mode 4 operation wm8198 production data w pd rev 4.0 june 2004 24 16.5 mclk periods mclk vsmp input video op[7:0] (del = 00) x x r a r b g a g b b a b b x x r a r b g a g b b a b b x x r a r b g a g b b a b b op[7:0] (del = 01) x x r a r b g a g b b a b b x x r a r b g a g b b a b b x x r a r b g a g b b a b b op[7:0] (del = 10) x x r a r b g a g b b a b b x x r a r b g a g b b a b b x x r a r b g a g b b a b b op[7:0] (del = 11) x x r a r b g a g b b a b b x x r a r b g a g b b a b b x x r a r b g a g b b a b b b a b b x x g a g b b a b b r a r b g a g b b a b b x x x x r a r b r a r b g a g b figure 22 mode 5 operation (mclk:vsmp ratio = 8:1) figure 23 mode 6 operation (mclk:vsmp ratio = 8:1) wm8198 production data w pd rev 4.0 june 2004 25 device configuration register map the following table describes the location of each control bit used to determine the operation of the wm8198. the register map is programmed by writing the required codes to the appropriate addresses via the serial interface. bit address wm8198 production data w pd rev 4.0 june 2004 26 register map description the following table describes the function of each of the control bits shown in table 5. register bit no bit name(s) default description 0 en 1 when selpd = 1 this bit has no effect. when selpd = 0 this bit controls the global power down: 0 = complete power down, 1 = fully active. 1 cds 1 select correlated double sampling mode: 0 = single ended mode, 1 = cds mode. 2 mono 0 mono/colour select: 0 = colour, 1 = monochrome operation. 3 selpd 0 selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by seldis[3:0]). offsets pga output to optimise the adc range for different polarity sensor output signals. zero differential pga input signal gives: 5:4 pgafs[1:0] 00 00 = zero output (use for bipolar video) 01 = zero output 10 = full-scale positive output (use for negative going video) 11 = full-scale negative output (use for positive going video) 6 mode4 0 required when operating in mode4: 0 = other modes, 1 = mode4. setup register 1 7 pgamode 0 selects between wide gain range pga mode (linear in db) and high resolution linear pga mode. 0 = wide gain range pga mode. gain (v/v) = 416/(566 ? pga[8:0]) 1 = high-resolution linear pga mode. gain (v/v) = 1 + pga[8:0]x4/511 determines the output data format. 1 muxop 1:0 00 = 8-bit multiplexed 01 = 8-bit multiplexed (8+8 bits) 10 = 8-bit multiplexed mode (8+8 bits) 11 = 4-bit multiplexed mode (4+4+4+4 bits) 2 invop 0 digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. 3 vrlcext 0 when set powers down the rlcdac, changing its output to hi-z, allowing vrlc/vbias to be externally driven. 5 rlcdacrng 1 sets the output range of the rlcdac. 0 = rlcdac ranges from 0 to avdd (approximately), 1 = rlcdac ranges from 0 to vrt (approximately). sets the output latency in adc clock periods. 1 adc clock period = 2 mclk periods except in mode 3 where 1 adc clock period = 3 mclk periods. setup register 2 7:6 del[1:0] 00 00 = minimum latency 01 = delay by one adc clock period 10 = delay by two adc clock periods 11 = delay by three adc clock periods 3:0 rlcv[3:0] 1111 controls rlcdac driving vrlc pin to define single ended signal reference voltage or reset level clamp voltage. see electrical characteristics section for ranges. cds mode reset timing adjust. 5:4 cdsref[1:0] 01 00 = advance 1 mclk period 01 = normal 10 = retard 1 mclk period 11 = retard 2 mclk periods monochrome mode channel select. setup register 3 7:6 chan[1:0] 00 00 = red channel select 01 = green channel select 10 = blue channel select 11 = reserved software reset any write to software reset causes all cells to be reset. it is recommended that a software reset be performed after a power-up before any other register writes. auto-cycle reset any write to auto-cycle reset causes the auto-cycle counter to reset to rinp. this function is only required when lin ebyline = 1. wm8198 production data w pd rev 4.0 june 2004 27 register bit no bit name(s) default description 0 linebyline 0 selects line by line operation 0 = normal operation, 1 = line by line operation. when line by line operation is selected mono is forced to 1 and chan[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. green and blue pgas are also disabled to save power. 1 acycnrlc 0 when linebyline = 0 this bit has no effect. when linebyline = 1 this bit determines the function of the rlc/acyc input pin and the input multiplexer and offset/gain register controls. 0 = rlc/acyc pin enabled for reset level clamp. internal selection of input and gain/offset multiplexers, 1 = auto-cycling enabled by pulsing the rlc/acyc input pin. see table 4, colour selection description in line-by-line mode for colour selection mode details. when auto-cycling is enabled, the rlc/acyc pin cannot be used for reset level clamping. the rlcint bit may be used instead. 2 fme 0 when linebyline = 0 this bit has no effect. when linebyline = 1 this bit controls the input force mux mode: 0 = no force mux, 1 = force mux mode. forces the input mux to be selected by fm[1:0] separately from gain and offset multiplexers. see table 4 for details. 3 rlcint 0 when linebyline = 1 and acycnrlc = 1 this bit is used to determine whether reset level clamping is used. 0 = rlc disabled, 1 = rlc enabled. 5:4 intm[1:0] 00 colour selection bits used in internal modes. 00 = red, 01 = green, 10 = blue and 11 = reserved. see table 4 for details. setup register 4 7:6 fm[1:0] 00 colour selection bits used in input force mux modes. 00 = rinp, 01 = ginp, 10 = binp and 11 = reserved. see table 4 for details. 0 vsmpdet 0 0 = normal operation, signal on vsmp input pin is applied directly to timing control block. 1 = programmable vsmp detect circuit is enabled. an internal synchronisation pulse is generated from signal applied to vsmp input pin and is applied to timing control block. 3:1 vdel[2:0] 000 when vsmpdet = 0 these bits have no effect. when vsmpdet = 1 these bits set a programmable delay from the detected edge of the signal applied to the vsmp pin. the internally generated pulse is delayed by vdel mclk periods from the detected edge. see figure 16, internal vsmp pulses generated for details. setup register 5 4 posnneg 0 when vsmpdet = 0 this bit has no effect. when vsmpdet = 1 this bit controls whether positive or negative edges are detected: 0 = negative edge on vsmp pin is detected and used to generate internal timing pulse. 1 = positive edge on vsmp pin is detected and used to generate internal timing pulse. see figure 16 for further details. setup register 6 3:0 seldis[3:0] 0000 selective power disable register - activated when selpd = 1. each bit disables respective cell when 1, enabled when 0. seldis[0] = red cds, pga seldis[1] = green cds, pga seldis[2] = blue cds, pga seldis[3] = adc special function 1 highspeed 0 0 = normal operation 1 = bias currents to analogue signal path increased to allow high speed operation wm8198 production data w pd rev 4.0 june 2004 28 register bit no bit name(s) default description offset dac (red) 7:0 dac[7:0] 0 red channel offset dac value offset dac (green) 7:0 dac[7:0] 0 green channel offset dac value offset dac (blue) 7:0 dac[7:0] 0 blue channel offset dac value offset dac (rgb) 7:0 dac[7:0] 0 a write to this register location causes the red, green and blue offset dac registers to be overwritten by the new value pga gain lsb (red) 0 pga[0] 0 this register bit forms the lsb of the red channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register 101000. pga gain lsb (green) 0 pga[0] 0 this register bit forms the lsb of the green channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register 101001. pga gain lsb (blue) 0 pga[0] 0 this register bit forms the lsb of the blue channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register 101010. pga gain lsb (rgb) 0 pga[0] 0 a write to this register location causes the red, green and blue pga lsb gain registers to be overwritten by the new value pga gain msbs (red) 7:0 pga[8:1] 0 bits 8 to 1 of red pga gain. combined with red lsb register bit to form complete pga gain code. when pgamode=0: pga gain (v/v) = 416/(566-pga[8:0) when pgamode=1: pga gain (v/v) = 1 + pga[8:0]x4/511 pga gain msbs (green) 7:0 pga[8:1] 0 bits 8 to 1 of red pga gain. combined with green lsb register bit to form complete pga gain code. when pgamode=0: pga gain (v/v) = 416/(566-pga[8:0) when pgamode=1: pga gain (v/v) = 1 + pga[8:0]x4/511 pga gain msbs (blue) 7:0 pga[8:1] 0 bits 8 to 1 of red pga gain. combined with blue lsb register bit to form complete pga gain code. when pgamode=0: pga gain (v/v) = 416/(566-pga[8:0) when pgamode=1: pga gain (v/v) = 1 + pga[8:0]x4/511 pga gain msbs (rgb) 7:0 pga[8:1] 0 a write to this register location causes the red, green and blue pga msb gain registers to be overwritten by the new value. table 6 register control bits wm8198 production data w pd rev 4.0 june 2004 29 applications information recommended external components 3 10 1 28 27 7 5 6 12 11 9 4 dvdd1 dvdd2 agnd1 rinp ginp binp mclk vsmp rlc/acyc sck sen sdi oeb 8 26 24 25 23 20 19 18 17 16 15 14 13 op[0] op[1] op[2] op[3] op[4] op[5] op[6] op[7]/sdo vrlc/vbias vrx vrt vrb avdd c2 c1 c6 c8 c4 c5 c7 c9 dvdd2 avdd video inputs timing signals interface controls output data bus dgnd agnd agnd agnd 22 dgnd 21 c3 agnd agnd2 2 c11 c10 dvdd2 c12 avdd ++ + dgnd agnd dvdd1 wm8198 c1-9 should be fitted as close to wm8198 as possible. notes: agnd and dgnd should be connected as close to wm8198 as possible. 1. 2. dvdd1 figure 24 external components diagram component reference suggested value description c1 100nf de-coupling for dvdd1. c2 100nf de-coupling for dvdd2. c3 100nf de-coupling for avdd. c4 10nf high frequency de-coupling between vrt and vrb. c5 1 f low frequency de-coupling between vrt and vrb (non-polarised). c6 100nf de-coupling for vrb. c7 100nf de-coupling for vrx. c8 100nf de-coupling for vrt. c9 100nf de-coupling for vrlc. c10 10 f reservoir capacitor for dvdd1. c11 10 f reservoir capacitor for dvdd2. c12 10 f reservoir capacitor for avdd. table 7 external components descriptions wm8198 production data w pd rev 4.0 june 2004 30 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ah. refer to this specification for further details. dm007.d ds: 28 pin ssop (10.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- 0.25 a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 9.90 10.20 10.50 e e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 a a2 a1 14 1 15 28 e1 e c l gauge plane 0.25 e b d seating plane -c- 0.10 c ref: jedec.95, mo-150 e 1 l 1 0.125 ref 0.65 bsc l 1 0 o 4 o 8 o wm8198 production data w pd rev 4.0 june 2004 31 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com |
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